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software selectable true bipolar input, 2-channel, 12-bit plus sign adc preliminary technical data ad7322* features ? 12-bit pl us sig n sar a d c ? t r ue bipolar analog inputs ? sof t w a r e se l e c t a b l e in pu t ran g e s 10v , 5v , 2 . 5v , 0 t o 10v ? t w o a n alog inputs with chan nel s e q u enc e r ? single ended , t r ue d i f f er entia l and p s e u do d i ff er entia l c a pability . ? high a n alog input impedanc e ? l o w p o w e r : - 6 mw ? f u ll p o w e r signal bandwidth: >13 mh z ? int e rnal 2.5 v r e f e r e nc e ? high speed s e r i al int e r f ace ? p o w e r down mo des ? 14-lead t ssop ? f o r 8 and 4 cha nnel equ i v a l e nt devic e s se e a d 7328 and ad73 24 respec tiv e ly . general description the ad7322 is a 2-cha n ne l , 12 -b i t p l us s i g n , 1 ms ps s u ccessi v e a p p r o x ima t ion ad c . th e ad c has a hig h sp e e d s e r i a l i n t e r f a c e t h at c a n o p e r at e at t h r o u g hp u t r a t e s u p t o 1 ms ps. the ad7322 can han d le t r ue b i p o la r analog in p u t sig n als. th e b i p o la r ra n g es ar e s o f t wa r e s e le c t a b le b y p r og ra mmin g t h e on b o a r d r a n g e re g i s t er . bi p o la r i n p u t ran g es i n cl ude 10v , 5v , 2.5v . the ad7322 ca n als o ha ndle a 0 t o 10 v uni p lo a r in p u t ra n g e , w h ich is a l s o s o f t wa r e s e le c t a b le . e a ch an a l og in p u t cha n n e l ca n b e i n de p e n d e n t l y pr o g r a mm e d to o n e o f t h e i n p u t ra n g es b y s e t t i n g t h e a p p r o p r i a t e b i ts i n t h e r a ng e reg i s t er . the ana l o g i n pu t c h a n nels ca n b e co nf igur e d a s sin g le-e nde d , f u l l y dif f e r en t i al o r p s eudo dif f er en t i al . d e dic a t e d c o n t r o l reg i st er b i ts a r e us e d t o co nf igu r e t h e analog i n p u ts. th e ad7322 co n t a i n s a cha n ne l s e q u en cer , al lo win g a u t o ma t i c co n v ersio n s be tw e e n e a ch a n al og in p u t c h ann e l . the ad c con t ain s a 2.5v i n t e r n al r e f e r e n c e . th e ad7322 als o al lo ws fo r e x t e rnal refer e n c e op era t ion. i f a 3 v ext e r n al r e fer e n c e is a p plie d to t h e ref i n/ out pin, t h e ad c can ha nd le a t r ue bi p o la r 12 v a n a l o g in p u t r a nge. mini m u m v dd and v ss s u p p lies o f 12v a r e r e q u ir ed f o r this 12 v in p u t ra n g e . * p a t e n t p e n d ing func tio n a l block di agram fi g u r e 1 . the s e r i a l clo c k f r e q uen c y , scl k , a p plie d t o t h e ad c w i l l det e r m i n e t h e maxim u m t h r o ug h p u t r a t e t h e ad c c a n op era t e a t . th e s c lk si g n al is us e d as t h e con v ersion clo c k an d als o t o t r a n sfer da t a t o a nd f r o m t h e a d c. th e s e r i al in t e r f ace is sp i tm , q s p i tm , m i c r o w i r e tm and d s p c o m p a t i b l e . the ad7322 o f f e rs p o w e r do wn m o des t o r e d u c e th e p o w e r co n s um p t i o n o f th e a d c a t lo w e r th r o ugh p u t ra t e s. produc t highlight s 1. th e ad7322 ca n accep t t r ue b i p o la r analog i n p u t sig n als, 10v , 5v , 2.5v a nd 0 t o 10v uni p ol a r sig n als. 2. t h e t w o an a l og i n p u ts ca n b e co n f igur ed as t w o s i n g le- en de d i n p u ts, on e t r ue dif f er en t i al o r one p s eudo dif f er en t i al i n p u t. th e ad7 322 has hig h i m p e dan c e analog i n p u ts. 3. th e ad7322 f e a t ur es a h i g h s p eed s e r i al i n ter f ace . thr o ug h p u t r a tes u p t o 1 ms ps ca n be achiev e d o n t h e ad7322. 4. l o w p o w e r , 1 2 mw a t maxim u m thr o ug h p u t ra t e o f 1 ms ps. in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the proper ty of th eir respectiv e co mpan ies. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . rev. pr e
ad7322 preliminary technical data t a ble of conte n ts ad7322s p ecif ica t io n s .................................................................. 3 a b s o l u t e m a xim u m r a t i n g s ............................................................ 6 p i n f u n c t i onal d e s c r i p t io n s ....................................................... 7 t e r m in olog y ...................................................................................... 8 the o r y o f o p era t io n . ....................................................................9 ad7322 r e g i s t ers . .......................................................................... 12 s e r i al in t e r f ace ................................................................................ 17 outline dime nsions .................................................................. 18 re visio n histo r y r e vision pre: pr e l imina r y v e rsio n r e v. pr e | pa g e 2 of 18
ad7322 preliminary technical data ad7322specifications 1 table 1. unless otherwise note d, v dd = + 4. 75 v to + 16.5 v , v ss = -4.75 v to C16.5v, v cc = 2. 7v to 5 . 25 v, v drive = 2.7v to 5.25v, v re f = 2.5 v i n ternal /external, f scl k = 20 mhz, f s = 1 msps t a = t max to t mi n p a r a m e t e r s p e c i f i c a t i o n unit s t e s t condition s / c o m m e n t s dynamic p e rf ormance f in = 50 khz sine wave signal to noise ratio (snr ) 2 78 db min differential mode 75 db min single-ended /pseudo differential mode signal to noise + distortion (sinad) 2 77 db min differential mode 74 db min single-ended/pseudo differential mode t o tal harmonic distortion (t hd) 2 - t b d d b m a x peak harmonic or spurious noise (sfdr) 2 -tbd db max intermodulation distortion (imd) 2 f a = 40.1 khz, f b = 41.5 khz second order terms -88 db typ third order ter m s - 8 8 d b t y p aperature delay 2 1 0 n s m a x aperature j i tter 2 5 0 p s t y p common mode rej e ction (cmrr) 2 t b d d b t y p channe l-to-cha nnel iso l ation 2 - 8 0 d b t y p f in = 400 khz full power ba nd wid t h 2 13 1.5 mhz typ mhz typ @ 3 db @ 0.1 db dc accuracy r e s o l u t i o n 1 2 + s i g n b i t s integral nonlinearity 2 1 . 5 l s b m a x differential non l inearity 2 0.95 lsb max guaranteed no missing codes to 13-bits offset error 3 6 lsb max unipolar range with straight binary output cod i ng offset error match 2 0 . 5 l s b m a x gain error 2 2 l s b m a x gain error match 2 0 . 6 l s b m a x positive full-sca l e error 2 2 lsb max bipol ar range w i th twos complement output c o ding positive full scale error match 2 0 . 6 l s b m a x bipol ar zero err o r 2 6 l s b m a x bipol ar zero err o r match 2 0 . 5 l s b m a x negative full scale error 2 2 lsb max negative full scale error match 2 0 . 5 l s b m a x analog in put input voltage ranges (programmed via range register) 10v 5v 2.5v 0 to 10v v o l t s v dd = +10v min , v ss = -10v min, v cc = 2.7v to 5.2 5 v v dd = +5v min, v ss = -5v min, v cc = 2.7v to 5.25v v dd = +5v min, v ss = - 5v min, v cc = 2.7v to 5.25 v v dd = +10v min, v ss = 0 v min, v cc = 2.7v to 5.25 v dc leakage current 10 na max input capacitance 8 pf typ wh en in track, 10v range 11 pf typ when in track, 5v, 0 to 10v range 19 pf typ when in t r ack, 2.5v range 6 pf typ when in hold referenc e in p u t/output input voltage range +2.5 to +3v v min to max input dc leakage current 1 a max input capactiance 20 pf typ reference output voltage 2.49/2.51 vmin/max reference temperature coefficient 25 ppm/c max r e v. pr e | pa g e 3 of 18
ad7322 preliminary technical data p a r a m e t e r s p e c i f i c a t i o n unit s t e s t condition s / c o m m e n t s reference output impedance 25 ? typ logic inputs input high volt age, v inh 0 . 7 * v drive v m i n input high volt age, v inl 0 . 3 * v drive v m a x input c u rrent, i in 1 a max v in = 0v or v cc input capacitance, c in 3 10 pf max logic outputs output high vol t age, v oh v drive - 0.2v v min i sou r ce = 200 a output low voltage, v ol 0 . 4 v m a x i sin k = 200 a floating state leakage current 1 a max floating state output capacitance 3 1 0 p f m a x outpu t coding straight natural binary cod i ng bit set to 1 in control r e gister tw o s complem e nt cod i ng bit set to 0 in control r e gister conversion r a te conversi on tim e 800 ns max 16 sclk cycles with sclk = 20 mhz track-and-hold acquisition tim e 150 ns max sine wave input 150 ns max full scale step i n put throughput rat e 1 msps max see serial interface section power requir emen ts digital inputs = 0v or v cc v dd 4.75v/+16.5v v m i n / m a x see v ss - 4 . 7 5 v / 1 6 . 5 v v m i n / m a x see v cc 2.7v / 5.25v v min/max see normal mode i dd 2 0 0 a m a x i ss 2 0 0 a m a x i cc 2 m a m a x auto-standby mode f sample = t b d i dd t b d a max i ss t b d a max i cc 1 . 6 m a t y p auto-standby mode f sample = t b d i dd t b d a max i ss t b d a max i cc 1 m a t y p ful l shutdow n mode i dd t b d a max i ss t b d a max i cc 1 a max sclk on or off power dissip a t ion normal mode 12 mw max v dd = +5v, v ss = -5v, v cc = 5v, table 5 table 5 table 5 notes 1 tem p era t ure ra n g es a s fo llow s : - 40c t o +85 c 2 se e te rmin ology 3 guaranteed by c h aracteriz a tion s p e c if icatio ns s u bj e c t to change witho ut no tice . r e v. pr e | pa g e 4 of 18
ad7322 preliminary technical data timing s p ecific a t ions table 2. unless otherwise note d, v dd = +4. 7 5 v to + 16. 5v, v ss = -4.7 5 to C1 6.5v, v cc = 2 .7v to 5.25, v dr ive =2.7v to 5.25, v ref = 2.5v in t e rnal/ e x t ernal , t a = t max to t min parameter limit at t min , t ma x u n i t d e s c r i p t i o n f sclk 1 0 k h z m i n 20 m h z m a x t con v ert 16t sclk n s m a x t sclk = 1/f sclk t qu iet 5 0 n s m a x minimum time between end of serial read and next falling edge of cs t 1 1 0 n s m i n minimum cs pulse wid t h t 2 1 0 n s m i n cs to sclk setup time t 3 2 0 n s m a x delay from cs until d ou t three-state disabled t 4 tbd ns max data access time after sclk falling edge. t 5 0 . 4 t sclk ns min sclk low pulsewidth t 6 0 . 4 t sclk ns min sclk high pulsewidth t 7 10 ns min sclk to data valid hold time t 8 25 ns max sclk falling edge to d out high i m pedance 10 ns min sclk falling edge to d out high i m pedance t 9 tbd ns min din set-up time prior to sclk falling edge t 10 5 ns min din hold time af ter sclk falling edge 1 s max power up from auto standby tbd s max power up from full shutdown/auto shut down mode f i gure 2. s e r i a l i n te r f ac e ti ming d i agr a m r e v. pr e | pa g e 5 of 18
ad7322 preliminary technical data absolute maximum ratings table 3. t a = 2 5 c, u n les s ot herwi s e not e d v dd to agnd, d g nd -0.3 v to +17.5 v v ss to agnd, dg nd +0.3 v to C17.5 v v cc to agnd, d g nd -0.3v to +7v v drive to v cc -0.3 v to v cc + 0. 3v v drive to agnd, dgnd -0.3 v to +7v agnd to dg nd -0.3 v to +0.3 v analog input voltage to agnd tbd digital input voltage to dgnd -0.3 v to +7 v digital output v o ltage to gnd -0.3 v to v drive +0 . 3 v ref in to agnd -0.3 v to v cc +0.3v input current to any pin except supplies 2 10ma operating temperature range -40c to +85c storage temperature range -65c to +150c unction tempe r ature +150c tssop package a thermal impedance 143 c/w c thermal impedance 45 c/w lead temperature, soldering reflow (10 C 3 0 sec) +235(-0/+5)c e s d t b d r e v. pr e pa g e 6 of 18
ad7322 preliminary technical data pin functi onal descr i ptions 14 13 12 11 9 top view (not to scale) 8 1 2 3 4 7 6 5 ad7322 din sclk refin/out v ss dgnd dout v in 1 10 v drive v in 0 agnd dgnd v dd f i gur e 3. ad73 22 p i n c o nfigu r a t i o n t ssop table 4. ad732 4 pin func tio n descriptions pin mnemonic pin number description s c l k 1 4 serial clock. log i c input. a se rial clock i n put prov ides the sc lk used for accessing the data from the ad732 2. this clock is also used as the clock source for t h e conver sion p r ocess. d ou t 1 2 serial data output. the conversi on output data i s suppl ied to this pin as a serial data stream. t h e bits are cloc ked out on the falling edge of the sclk input and 16 sclks are r e quired to access the data. the data stream consist s of two leading zero s, o n e chann e l iden tification bit, a sign bit follow e d by 12 bits of c o nversi on data. the data is prov ided msb first. s ee the serial interface section. cs 1 chip select. acti ve low logic input. this inp ut pr ovides the dual function of initiating conver sions on the ad7322 and frames the serial data transfer. d i n 2 data in. data to be written to the on-chip register s is provided on this in put an d is clocked into the register on the falling edge of sclk. see register section. a g n d 4 analog ground. ground reference point for all an alog circuitry on the ad7322. a ll analog input signal s and any external refere n c e signal sh ould be referred to t h is agnd voltage. ref in/ ref out 5 reference input/ reference output pin. when en abled the on-c hip reference i s avail a ble on this pin for use external to th e ad7322. altern ativley, the inte rnal reference can be disabled and an external reference appl ie d to this input. when usin g the ad7322 with an external reference, the in ternal reference must be di sable d via the control register. the nominal reference vo ltage is 2.5 v, which appear s at the p i n. t h e default on power up is for external reference oper a tion. see . v cc 1 0 analog supply voltage, 2.7 v to 5.25 v. this is th e supply voltag e for the adc core on the ad7322. this supply should be decoupled to agnd. v dd 9 positive po wer supply voltage. this is the po si tive supply voltag e for the analog input section. v ss 6 negative power supply voltage. this is the ne ga vtive supply voltage for the analog input section. dgnd 3,13 this is the digital ground pin. v drive 1 1 logic power supply input. the voltage applied to this pin determines the operating voltge of the sertial intefa ce. v i n 0 - v i n 1 7 , 8 analog input 0 through analog i n put 1. the an alog inputs are multiplex e d into the on-chip track-and-hold. the analog in put channel for c o nversion is se lec t ed by programming the channe l address bit add0, in the control register . the inputs can be configured as 2 single- ended inputs, 1 true differential input pair, 1 pseudo differential inputs. the configuration of the analog inpu ts is selected by programmin g t h e mode bits, mode1 and mode 0, in the control register . the input range on each in put channe l is controlled by progra mming the range register. inputs ranges of 10v, 5v, 2.5 v and 0 to 10v can be se lected on each an alog input channe l. see register section. table 8 r e v. pr e | pa g e 7 of 18
ad7322 preliminary technical data terminology d i f f erenti a l n o n l i n e a r i ty this is t h e dif f er en ce b e tw e e n t h e m e as ur e d a nd t h e ide a l 1 l s b c h a n g e be tw een a n y tw o a d j a cen t cod e s i n t h e a d c . in t e g r a l no n l i n e a r i t y this is t h e maxi m u m d e v i a t io n f r o m a st ra ig h t l i ne p a ssin g th r o ugh th e en d p o i n t s o f th e ad c tra n sf e r fun c ti o n . th e e n d p oi n t s of t h e t r ans f e r f u nc t i on are z e ro s c a l e, a p o i n t 1 l s b b e lo w t h e f i rst c o de t r a n si t i o n , and f u l l s c a l e, a p o in t 1 l s b a b o v e t h e las t c o de t r a n si t i o n . off s et c o de e r r o r this a p plies t o s t ra ig h t bina r y o u t p ut co d i n g . i t is t h e de v i a t ion o f th e f i rs t co de tra n si tio n (00 . . . 000) t o (00 . . . 001) f r o m th e ide a l, i . e . , a g n d + 1 ls b . off s et e r r o r ma t c h this is t h e dif f er en ce i n of fs et er r o r b e tw e e n an y tw o i n p u t chan nel s . ga in er r o r this a p plies t o s t ra ig h t bina r y o u t p ut co d i n g . i t is t h e de v i a t ion o f th e las t co de tra n si tion (111 . . . 110) t o (111 . . . 111) f r o m the ideal (i .e ., 4 x vref C 1 ls b , 2 x v ref C1 ls b , v ref C1 ls b) a f t e r t h e o f fs et er r o r has b e en ad j u s t e d o u t. ga in er r o r m a t c h this is t h e d i f f er en ce i n g a in e r r o r b e tw e e n an y tw o in p u t chan nel s chan nel s . b i p o l a r z e ro c o d e e r ro r this a p plies w h en usin g tw os c o m p le m e n t o u t p u t co d i n g and a b i p o la r ana l og i n p u t. i t is t h e d e v i a t ion o f t h e mids ca le tra n si ti o n (all 1s t o all 0s) f r o m th e i d eal v in volt age, i. e. , a g n d - 1 ls b . b i p o l a r z e ro c o d e e r ro r match t h i s re f e r s to t h e d i f f e r e n c e i n bip o l a r z e ro c o d e e r ror b e tw e e n an y two in p u t ch a n n e l s . po s i t i v e f u l l s c a l e e r r o r this a p plies w h en usin g tw os c o m p le m e n t o u t p u t co d i n g and a n y o f th e b i po la r a n alog i n p u t ra n g e s . i t i s th e d e vi a t i o n o f th e las t c o de tra n s i t i o n (011110) t o (011111) f r o m th e ideal ( +4 x v ref - 1 l s b , + 2 x v ref C 1 ls b , + v ref C 1 ls b) a f t e r t h e bip o l a r z e ro c o d e e r ror h a s b e e n a d j u s t e d out . po s i t i v e f u l l s c a l e e r r o r m a t c h this is t h e dif f er en ce i n p o si t i ve f u l l s c ale er r o r b e twe e n an y tw o in p u t chann e ls. ne g a t i v e fu l l s c a l e e r r o r this a p plies w h en usin g tw os c o m p le m e n t o u t p u t co d i n g and a n y o f t h e b i p o l a r ana l og i n p u t ra n g es. this is t h e d e v i a t io n o f th e f i rs t co de tr a n si tion (100 00) t o (10001) f r o m th e ideal (i .e ., - 4 x v ref + 1 ls b , - 2 x v ref + 1 ls b , - v ref + 1 ls b) a f t e r th e b i p o la r z e r o c o d e er r o r h a s be en ad j u s t e d o u t. ne g a t i v e fu l l s c a l e e r r o r m a t c h this is t h e dif f er en ce i n n e ga t i v e f u l l s c ale er r o r b e twe e n an y tw o in p u t chann e ls. t r a c k-a nd-h o l d a c q u i s iti o n t i me the t r ack - an d - h o ld am plif ier r e t u r n s in t o t r ack m o de a f t e r t h e f i f t e e n t h scl k fa l l in g e d ge . t r a c k-and- h o ld ac q u isi t io n t i m e is th e tim e r e q u i r e d f o r th e o u t p u t o f th e tra c k - a n d - h o ld a m p l i f i e r t o r e ac h i t s f i na l val u e , wi thin 1/2 ls b , a f t e r t h e end o f co n v ersio n . si g n a l to ( n oi s e + d i s t or t i on ) r a t i o t h i s i s t h e me a s u r e d r a t i o of s i g n a l to ( n oi s e + d i stor t i on ) a t t h e o u t p ut o f t h e a/ d co n v er t e r . the sig n al is t h e r m s a m pl i t u d e of t h e f u ndam e n t a l . n o is e is t h e su m o f a l l n o n-f u ndam e n t a l sig n als u p t o half th e s a m p l i n g f r e q uen c y (f s /2), excl udin g dc. the ra t i o is de p e n d e n t on t h e n u m b er o f q u an t i za t i o n l e v e l s i n th e di gi t i za ti o n p r oce s s; th e m o r e lev e l s, th e smalle r th e q u a n tiz a ti o n n o i s e . th e t h eo r e tical si gn al t o (n o i se + d i s t o r ti o n ) ra tio f o r a n id ea l n-b i t co n v er t e r wi t h a sin e wa v e in p u t is gi v e n by : s i g n a l t o (n o i se + d i s t o r ti o n ) = (6. 0 2 n + 1. 7 6 ) db th us f o r a 13-b i t co n v er t e r , this is 80.02 db . t o t a l ha r m on i c d i s t or t i on t o tal ha rm o n i c d i s t o r ti o n (t hd ) i s th e ra ti o o f th e rm s s u m o f ha r m o n ics t o the f u ndam e n t al . f o r th e ad7322 i t is def i n e d as: 1 2 6 2 5 2 4 2 3 2 2 log 20 ) ( v v v v v v db thd + + + + = w h er e v 1 is t h e r m s a m pli t ude o f t h e f u ndam e n t a l and v 2 , v 3 , v 4 , v 5 a nd v 6 a r e t h e r m s am pli t udes o f t h e s e c o nd t h r o ug h t h e six t h ha r m o n i c s . p e a k h a rmo n i c o r s p uri o us n o is e p e a k ha r m o n ic o r sp ur io us n o is e is def i ne d as t h e r a t i o o f t h e r m s val u e o f t h e n e xt la rg es t com p on e n t i n t h e ad c o u t p ut s p e c t r um (u p t o fs/2 a nd excl udin g dc) t o t h e r m s val u e o f t h e f u ndam e n t a l . n o r m a l ly , t h e va lue o f t h is sp e c if ica t ion is det e r m i n e d b y t h e la rg es t ha r m o n ic in t h e sp e c t r um, b u t fo r ad cs w h er e t h e ha r m o n ic s a r e b u r i e d i n t h e no is e f l o o r , i t wi l l be a n o ise pea k . ch a n n e l - t o - c h a n n e l i s o l a t i o n c h a n n e l - t o -channe l is ol a t ion is a m e asur e o f t h e le v e l o f cr osst a l k b e twe e n an y tw o channels. i t is m e asur e d b y a p ply i ng a f u l l -s cale , 400 kh z sin e wa v e s i g n al t o al l un s e lec t ed in p u t cha n n e ls an d de t e r m inin g h o w m u ch t h a t sig n a l is a t t e n u a t e d i n r e v. pr e | pa g e 8 of 18
preliminary technical data ad7322 t h e s e le c t e d channel wi t h a 50 k h z sig n a l . t h e f i gur e g i ven is th e w o rs t-c a s e acr o s s al l eig h t cha n n e ls f o r th e ad7322. inte r m o d u l at i o n d i s t or t i on w i t h i n p u ts co nsist i n g o f sine w a ves a t tw o f r e q uen c ies, fa and f b , an y a c t i ve d e v i c e w i t h no n - l i ne ar i t i e s w i l l c r e a te d i stor t i on p r o d uc ts a t s u m a nd dif f er ence f r e q uen c ies o f mfa nfb w h er e m, n = 0, 1, 2, 3, et c. i n ter m o d u l a t io n dis t o r tion t e r m s a r e th os e f o r whic h n e i t her m n o r n a r e e q ual t o zer o . f o r exa m p l e , th e seco n d o r der t e r m s in c l ude (fa + fb) a nd (fa C f b ), while t h e thir d o r der t e r m s in c l ude (2fa + fb), (2fa C fb), (fa + 2fb) a nd (f a C 2fb). the ad7322 is t e s t e d usin g t h e ccif s t anda rd wher e tw o in p u t f r e q u e nc i e s ne a r t h e top e n d of t h e i n put b a nd w i d t h are u s e d . i n t h is c a s e , t h e s e con d o r der te r m s a r e usua l l y dist an c e d i n f r e q uen c y f r o m t h e o r ig ina l si n e wa v e s w h i l e t h e t h ir d o r der t e r m s a r e us ual l y a t a f r eq uen c y c l os e t o th e in p u t f r eq uen c ies. a s a r e su lt, t h e s e co nd and t h ir d o r der ter m s a r e sp e c if ie d s e p a r a tely . t h e ca lc u l a t ion o f t h e i n ter m o d u l a t io n disto r t i o n is as p e r t h e thd s p e c if ic a t ion w h er e i t is t h e ra t i o o f t h e r m s s u m o f th e in d i v i d u al d i s t o r ti o n p r od uct s t o th e rm s a m p l i t ud e o f t h e s u m o f t h e f u ndam e n t als exp r es s e d i n db s. ps r (p o w e r s u p p ly reje c t i o n) v a ri a t i o n s in po w e r s u p p l y w i ll a f f e ct th e full- s cale tra n si ti o n b u t n o t t h e con v er t e r s lin e a r i t y . p o w e r su p p ly r e je c t io n is t h e max i m u m cha n ge in f u l l -s ca le t r a n si t i o n p o i n t d u e to a chan ge in p o w e r s u p p l y v o l t a g e f r o m t h e n o minal va l u e. s e e t y p i cal p e r f o r ma n c e c u r v es. theory of op eration circuit informa t ion the ad7322 is a fast, 2-cha n nel , 12-b i t p l us s i g n , b i p o la r i n p u t, s e r i al a/d con v er t e r . th e ad73 22 ca n ac cep t b i p o la r in p u t ra n g es tha t in cl ude 10v , 5v , 2.5v , i t c a n als o accep t 0 t o 10 v uni p ol a r in p u t ra n g e . dif f er en t ana l og in p u t ran g es can b e p r ogra m m e d o n eac h a n alog in p u t cha n n e l via th e o n -ch i p ra n g e r e g i s t er . th e ad7322 has a hig h s p e e d s e r i al in t e r f ace tha t ca n op era t e a t t h r o ug h p u t ra t e s u p t o 1 ms ps. the ad7322 r e q u ir es v dd and v ss du a l su p p l i e s for t h e hig h v o l t a g e analog i n p u t s t r u c t ur e . th e s e s u p p lies m u s t b e e q ual to o r gr ea t e r th a n t h e a n alog i n p u t ra n g e . s e e fo r t h e mini m u m r e q u i r em e n ts o n t h es e s u p p lies fo r e a ch analog i n pu t r a n g e . th e ad7322 r e q u ir es a lo w v o l t a g e 2.7 v t o 5.25 v v cc su p p ly to p o we r t h e a d c c o re . ta b l e 5 table 5. refere nce and s u pply require m e n ts f o r each a n alog input rang e ai n r a n g e v dd /v ss min v cc r e f e re n c e v 12 v 12 v 3 v t o 5v 3v 10 v 10v 3 v t o 5 v 2.5 v 5 v 5 v 3v t o 5v 2.5 v 2.5 v 5 v 3 v t o 5 v 2.5 v 0 t o 10 v 10 v 3 v t o 5 v 2.5 v the analog i n pu ts can b e co nf i g ur e d as ei t h er 2 sin g le-e n d e d in p u ts, 1 t r ue dif f er en t i al i n p u t s , o r 1 p s eudo dif f er en t i al i n p u t. s e le c t ion ca n b e m a de b y p r o g r a mmin g t h e m o de b i ts, m o de0 an d m o de1, in t h e on-chi p c o n t r o l r e g i ster . the s e r i al clo c k in p u t acces s es da t a f r o m t h e p a r t b u t als o p r o v ides t h e clo c k s o ur ce fo r e a ch s u cces si ve a p p r o x ima t ion ad c. th e ad7 322 has a n on-chi p 2.5 v r e f e r e n c e . i f an e x t e r n al refer e n c e is t h e p r efer r e d o p t i o n t h e us er m u s t wr i t e t o t h e r e fer e nce b i t in t h e con t r o l r e g i s t er t o dis a b l e t h e in t e r n al refer e nce . the ad7322 als o f e a t ur es p o w e r - do wn o p tio n s t o al lo w p o w e r s a v i n g be tw e e n co n v ersio n s. the p o w e r - do wn m o de s a r e s e le c t e d b y p r o g ra mmin g t h e p o w e r ma na ge m e n t b i ts in t h e on - chi p c o n t r o l r e g i s t er , as des c r i b e d in t h e m o des o f o p era t io n secti o n . c o n v ert e r o p er a t ion the ad7322 is a s u cces si v e a p p r o x ima t ion a n alog-t o-dig i tal co n v er t e r , bas e d a r o u n d tw o c a p a ci ti v e d a cs. f a n d s h o w s i m p l i f i e d s c h e m a ti cs o f th e ad c s i n si n g le en d e d m o d e d u r i n g t h e ac q u isi t io n an d co n v ersio n phas e, re sp e c t i vely . and fi show s i m p l i f i e d s c he m a t i c s o f t h e a d c i n dif f er en t i a l m o de d u r i n g ac q u i s i t io n and c o n v e r s i on ph as e, re sp e c t i vely . t h e a d c i s c o m p r i s e d of co n t r o l log i c, a sar , an d a c a p a ci t i ve d a c. i n f ( t h e acq u isi t ion pha s e), sw2 is clos e d and sw1 is i n p o si t i on a, t h e co m p a r a t o r is he ld in a ba lan c e d con d i t io n, and the s a m p lin g ca p a c i t o r a r ra y acq u ir es t h e sig n al o n t h e i n p u t . i gur e 4 i gur e 4 f i gure 4. adc a c qu isition p h ase(single ended) fi g u r e 5 f i g u re 6 g u re 7 r e v. pr e | pa g e 9 of 18
ad7322 preliminary technical data w h en t h e ad c s t a r ts a con v ersio n ( ) , sw2 wi l l o p e n a nd s w 1 wil l mo v e t o p o si tio n b , ca usin g t h e c o m p a r a t o r t o be come un balan c e d . th e con t rol log i c a n d t h e c h a r g e r e dist r i b u t i o n d a c is us e d to a dd and sub t r a c t f i xe d a m o u n t s o f c h a r g e f r o m th e s a m p lin g c a p a ci t o r a r ra ys t o b r in g t h e c o m p ar a t or b a c k i n to a b a l a nc e d c o nd i t i o n . whe n t h e co m p a r a t o r is r e b a lan c e d , t h e c o n v ersio n is com p let e . the co n t r o l l o g i c g e n e r a t e s t h e a d c o u t p u t c o d e . f igur e 5 f i gure 5. adc con v ersion p h ase(single ended)

f i gur e 6 f i gure 6. adc d i ffe r e ntial c o nfig ur ation du ring ac qu isition p h ase

s h o w s th e di f f e r e n ti a l co n f i g ura t i o n d u ri n g th e a c q u isi t ion p h as e . f o r th e c o n v ersio n p h as e , s w 3 wil l o p en, sw1 and sw2 wil l m o v e t o p o si tio n b , s e e . th e o u t p u t im p e d a n c es o f t h e s o ur ce dr i v i n g t h e v i n+ an d v i n- pin s m u st b e ma t c h e d; o t her w is e t h e t w o i n p u ts wi l l ha v e dif f er en t s e t t ling t i me s , re su lt i n g i n e r ror s . f i g u r e 7 f i gure 7. adc d i ffe r e ntial c o nfig ur at i o n du ring conve r s i on p h as e

ou t p u t c o d i n g the ad7322 defa u l t o u t p u t co din g is s e t t o tw o s co m p lem e n t . the o u t p u t co din g is co n t r o l l ed b y th e c o din g b i t in the c o n t r o l r e gi s t er . t o c h a n g e t h e o u t p u t cod i n g t o s t ra i g h t bina r y c o din g t h e c o din g b i t i n t h e c o n t r o l r e g i ster m u st b e s e t. w h en op era t in g i n s e q u en c e m o de t h e o u t p u t co din g fo r e a ch cha n ne l i n t h e s e q u e n ce wi l l b e t h e val u e w r i t t e n t o t h e co din g b i t d u r i n g t h e last wr i t e t o t h e c o n t r o l reg i st er . tr a n s f e r f u n c t i o n s the desig n e d c o de tra n si t i o n s o c c u r a t s u cces s i v e in t e g e r l s b va l u es (i .e., 1 lsb , 2 ls b , a nd s o o n ). the ls b si ze is de p e ndan t o n t h e analog i n p u t r a n g e s e le c t e d . table 6. lsb s i zes for each a n al og input range i n p u t r a n g e f u l l s c a l e r a n g e/4096 ls b s i z e 1 0 v 2 0 v / 4 0 9 6 4 . 8 8 2 m v 5 v 1 0 v / 4 0 9 6 2 . 4 4 1 m v 2 . 5 v 5 v / 4 0 9 6 1 . 2 2 m v 0 t o 10v 10v/4096 2.441 mv the ideal tran sf er c h a r ac t e r i s t ic f o r th e ad7322 when t w os c o m p lemen t c o din g is s e lec t e d is s h o w n i n , a n d t h e ideal tra n sf er c h a r ac t e r i s t ic f o r th e ad7322 w h en s t ra ig h t bina r y co din g i s s e le c t e d is sh o w n i n . f i g u r e 8 f i g u re 8. t w os co m p le ment t r ans f er c h ar ac t e ris t i c (b ipo l ar r a ng es ) f i gur e 9 f i gur e 9 . str a i g ht bi na r y t r a n sfe r char a c t e r i stic (bi p ol ar ra nge s ) 000...000 - fsr/2 + 1l sb a d c code a n a l og input 011...111 100...001 100...010 011...110 000...001 111...111 +f s r / 2 - 1l sb 100...000 v ref - 1l sb 000...000 -fsr/2 a dc code a n a l og input 111...111 000...001 000...010 111...110 111...000 011...111 1l sb fsr/2 -1l s b anal og inp u t the a n alog in p u ts o f th e ad73 22 ma y b e co nf igur ed as s i n g le- en de d , t r ue dif f er en t i al o r p s e u do dif f er en t i al vi a t h e c o n t r o l reg i st er m o de b i ts as sh own in o f t h e reg i st er s e c t ion. the ad7322 can accep t t r ue b i p o la r in p u t sig n als. on p o w e r u p t h e analog in p u ts wi l l op era t e as 2 sin g le-e n d e d analog i n p u t c h a n ne ls. i f t r ue dif f er e n t i al o r p s eudo dif f er en t i al is re qu i r e d , a w r it e to t h e c o n t ro l re g i ste r i s n e c e ss ar y to ch ange t h is co nf igura t i o n a f t e r p o w e r u p . ta b l e 9 f i g u re 1 0 show s t h e e q u i v a l e n t a n a l o g i n put c i rc u i t of t h e ad7322 in s i n g le-ende d m o de . s h o w s th e e q ui valen t analog in p u t s t r u c t ur e in dif f er en t i al mo de . th e t w o dio d es prov i d e e s d pr ote c t i on f o r t h e a n a l o g i n put s . f i gur e 1 1 r e v. pr e | pa g e 10 o f 18
preliminary technical data ad7322 d d v dd c2 r1 vin0 v ss c1 f i g u re 10. equiv a le nt a n al og input c i rcuit - (sing l e e n d e d) f i gur e 10 d d v dd c2 r1 vin+ v ss c1 d d v dd c2 r1 vin- v ss c1 f i g u re 11. equiv a le nt a n al og input c i rcuit - ( d if f e r e nt i a l) f i gur e 1 1 c a r e s h o u ld b e t a k e n t o ens u r e t h e analog i n pu t ne v e r exce e d s th e v dd a nd v ss s u p p l y ra ils b y m o r e than 300 mv . this wil l ca us e t h e dio d e s to b e come fo r w a r d b i as e d and st a r t co n d ucti n g in t o e i th e r th e v dd or v ss ra il s . t h ese d i od es ca n co nd uc t u p t o 1 0 ma wi t h o u t c a usin g ir r e v e rsib le d a ma ge t o th e pa r t . the c a p a c i t o r c1, i n a n d i s t y p i cal l y 4 pf a nd can p r ima r i l y b e a t t r ib u t e d to p i n ca p a c i t a nce. t h e r e sisto r r1, is a l u m p e d co m p on e n t made u p o f t h e on- r esis t a n c e o f t h e i n p u t m u l t i p le x e r a n d th e tra c k- a n d- h o ld sw i t ch . th e c a pa ci t o r c2, is th e s a m p l i n g c a p a ci t o r , i t s ca p a ci tan c e wil l va r y dep e n d in g on t h e an a l og in p u t ra n g e s e le c t e d . t r a c k-a nd-h o l d s e c t i o n the t r ack-and-h o ld o n t h e analog i n p u t o f the ad7322 al lo ws th e ad c t o acc u ra t e l y con v er t a n in p u t sine wa v e o f f u l l s c ale a m pli t ude t o 13-bi t acc u rac y . th e i n p u t b a nd w i d t h o f t h e t r ack - an d - h o l d is g r e a t e r t h an t h e n y q u ist ra te o f t h e ad c , th e ad7322 c a n ha ndle f r eq uencies u p t o 13 mh z. the t r ack-and- h o ld en ters i t s t r ack i n g m o d e o n t h e 15 th scl k fallin g edg e a f t e r th e cs fa l l in g e d ge . the t i m e r e quir e d t o acq u ir e an in p u t sig n a l w i l l dep e nd o n h o w q u i c k l y t h e s a m p ling c a p a ci t o r is c h a r g e d . w i t h zer o s o ur ce im p e dan c e 30 0 n s w i l l b e s u f f i cien t t o ac q u ir e t h e sig n al t o t h e 13-b i t le ve l . the acq u isi t io n t i me r e q u ir e d is ca lc u l a t e d using t h e fol l o w in g fo r m u l a: t ac q = 10 x ((r so u r ce + r) c) w h er e c is t h e s a m p ling c a p a ci t a nce and r is t h e r e sis t an c e s e en b y t h e t r ack-and- h o ld am plif ier lo ok in g b a ck o n t h e in put. f o r th e ad7322 , th e val u e o f r wil l in c l ude the o n -r esis tan c e o f th e in p u t m u l t i p lexer . th e va l u e o f r is typ i cal l y 300 ? . r so ur c e s h o u ld i n cl ude a n y ext r a s o ur c e im p e dan c e on t h e analog in p u t. t y p i c a l c o nnec t i o n di a g r a m f i gur e 1 2 f i gur e 1 2 f i g u re 12. t y pic a l conne c t io n d i ag r a m s h o w s a typ i cal co nn e c tio n dia g ram f o r th e ad7322. i n t h is co nf igur a t io n t h e a g n d p i n is con n e c t e d t o t h e ana l og g r o u n d pl an e o f t h e sys t em. the d g nd p i n is c o nn e c t e d t o t h e dig i t a l g r o u n d plan e o f t h e sys t em. th e analog i n p u ts o n t h e ad7322 can be co nf igur ed t o op era t e in sin g le en ded , t r ue dif f er en tial o r p s eudo dif f er en tial m o de . th e ad7322 can o p era t e w i t h e i t h er t h e i n t e r n al o r a n ext e r n al r e fer e n c e . i n , th e ad7322 is co nf ig ur ed t o o p era t e wi t h t h e in t e r n a l 2.5v r e f e r e n c e . a 470 nf deco u p lin g c a p a ci t o r is r e q u ir ed w h en o p era t i n g wi t h t h e i n t e r n al r e fer e n c e . the v cc p i n can be co nnec t e d to ei th er a 3 v o r a 5v s u p p l y vol t age. t h e v dd and v ss a r e t h e d u a l s u p p lies fo r t h e hig h v o l t a g e a n alog in p u t s t r u c t ur es. the v o l t a g e o n t h es e pin s m u s t b e e q u a l to or g r e a te r t h an t h e h i g h e s t ana l o g i n put r a nge s e le c t e d o n t h e a n alog in p u t c h a nne ls, s e e fo r mo r e info r m a t io n. t h e v dr iv e p i n is c o nn e c te d to t h e su p p ly vol t a g e of t h e m i c r opro c e ss or . t h e vo lt age appl i e d to t h e v dr iv e in p u t co n t r o ls t h e v o l t a g e a t w h ich t h e s e r i al in t e r f ac e o p era t e s . ta b l e 5 r e v. pr e | pa g e 11 o f 18
ad7322 preliminary technical data ad7322 registers the ad7322 has tw o-p r og ra mma b le r e g i s t ers, th e co n t r o l r e g i s t e r and t h e ra n g e r e g i s t e r . th e s e r e g i s t ers a r e wr i t e o n l y r e g i s t ers. a d dressin g the s e r e g i st e r s a s e r i al tra n sf er o n the ad7322 co n s is ts o f 16 sclk c y c l es. th e thr e e ms bs o n th e d i n lin e d u r i n g eac h 16 sclk tra n sf er a r e dec od ed t o det e r m i n e w h ich r e g i s t er is addr es s e d . th e t h r e e ms bs co n s ists o f t h e w r i t e b i t, zer o b i t and a reg i st er s e le c t b i t. th e reg i st er s e l e ct b i t is us e d t o det e r m i n e w h ich o f t h e t w o on- b o a r d r e g i s t ers is s e le c t e d . the w r i t e b i t wi l l deter m i n e if t h e d a t a o n t h e d i n li n e fol l o w ing t h e reg i st er s e le c t b i t is lo ade d i n t o t h e addr es s e d r e g i s t er o r no t. i f t h e w r i t e b i t is 1 t h e b i ts wil l b e lo ade d i n t o t h e r eg ister addr ess e d b y t h e reg i st er s e le c t b i t. i f t h e w r i t e bi t is a 0 t h e da t a on t h e d i n wi l l n o t b e lo ade d in t o an y r e g i s t er an d b o t h r e g i s t ers w i ll r e m a i n un c h an g e d. ta ble 7. d e co di ng reg i ster se le ct bit an d wr ite bit. wr i t e zer o re g i ster s e l e c t 2 co m m e n t 0 0 0 da t a o n t h e d i n lin e d u r i n g this s e r i al tra n sf er wil l be ig n o r e d . reg i st er co n t en ts wil l re m a i n u n ch a n ge d. 1 0 0 this com b ina t io n s e lec t s the c o n t r o l reg i s t er . t h e s u b s eq uen t 12 b i t s will b e l o a d ed in t o t h e c o n t r o l reg i s t er . 1 0 1 this com b ina t i o n s e le c t s t h e r a n g e reg i st er . th e subs e q uen t 8 b i t s w i l l b e lo ade d i n t o t h e r a n g e reg i st er . co n t r o l r e g i s t e r the c o n t r o l r e g i s t er is us e d t o s e le c t t h e analo g i n p u t co nf igu r a t io n, refer e n c e, c o ding, p o w e r m o de etc. t h e c o n t r o l reg i ste r is a wr i t e o n l y 12-b i t r e g i s t er . da t a lo ade d o n t h e d i n lin e co r r es p o n d s t o th e ad7322 co nf igura t io n fo r th e n e xt con v ersio n . da t a sh ou ld be lo ade d in t o t h e c o n t r o l reg i st e r a f t e r t h e r a n g e reg i s t er has b e en ini t iali ze d . the b i t f u n c t i on s o f t h e c o n t rol reg i st er a r e o ut l i ne d i n . ta b l e 8 ta ble 8. co ntr o l regis t er control regis t er (t he power-up status of all bits is 0) ms b d b 14 d b 1 3 d b 1 2 d b 1 1 d b 1 0 d b 9 d b 8 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 wr i t e zer o re g i st er se l e c t zer o z e r o ad d 0 m o d e 1 m o d e 0 p m 1 p m 0 c o din g r e f s e q 1 s e q 2 zer o b i t m n e m o n i c c o m m e n t 1 0 a d d 0 t h is channel ad d r ess bit is used to select the an alog in put chan nel for the next conver sion if th e sequencer is not being used. 9, 8 mode1, mode0 these two mode bits are used to se lect the configuation on the two an alog input pins. they are used in conjunction wit h the channe l address bit. on the ad7322 the analog inputs can be configure d as either 2 single ended inputs, 1 fully diff erential input, 1 pseudo differential input. see . 7 , 6 p m 1 , p m 0 power manage ment bits. these two bits are use d to se lect differ e nt power mod e options on the ad7322. see . 5 c o d i n g this bit is used to select the type of output codi ng the ad7322 will use for the next conver sion result. if the coding = 0 then the output codi ng wi ll be 2 s co mplement. if co d i ng = 1, then the output cod i ng will be straight binary. when operating in sequence m o de th e output coding for each channe l will be t h e value written to the coding bit during the last write to the control register. 4 r e f reference bit. this bit is used to en able or disable the internal re ference. if this ref = 0 then the i n ternal reference will b e enable and used for the next conversi on. if ref = 1 then an external reference will be used for the next con version and the internal referen c e wi ll be disab l ed. when opera ting in sequenc e mode the table 9 table 10 r e v. pr e | pa g e 12 o f 18
preliminary technical data ad7322 reference used for each cha nne l will be the valu e writte n to the ref bit during th e last write to the control register. 3,2 seq1/seq2 the sequence 1 and sequence 2 bits are used to control the o p er ation of the sequencer. see table 8 14,12,11,1 zero a zero must be written to this bit to ensure correct operation of the ad7322. ta ble 9. a n alog input conf igur atio n select ion channel a ddre ss b i t mo de1 =1, mo de0 = 1 mo de1 = 1, mo de0 =0 mo de1 = 0, mo de0 =1 mo de1 =0, mo de0 =0 1 pseud o differential i/p 1fully differential i/p not allowed t w o-single end e d i/ps a d d 0 v i n + v i n - v i n + v i n - v i n + v i n - 0 v i n 0 v i n 1 v i n 0 v i n 1 v i n 0 a g n d 1 v i n 0 v i n 1 v i n 0 v i n 1 v i n 1 a g n d table 10. power mode selec t ion p m 1 p m 0 d e s cri p t io n 1 1 f u l l s h u t do wn m o de , i n th i s m o d e all in t e rn al ci r c ui tr y o n th e ad7322 is p o w e r e d do wn. i n f o r m a t io n in t h e c o n t r o l r e g i s t er is r e t a in e d wh en t h e ad7322 is in f u l l s h u t do wn m o de. 1 0 a u t o s h u t do wn m o de , th e ad7322 wi l l en ter f u l l s h u t do wn a t t h e en d o f e a ch co n v er sio n wh en t h e co n t r o l r e gis t er is u p da te d . al l in ter n a l cir c ui t r y is p o w e r e d do wn in f u l l sh utd o w n . 0 1 au t o s t a n d b y m o d e , i n th i s m o d e all in t e rn al ci r c ui tr y i s p o w e r e d do wn ex cl udin g t h e in ter n a l r e f e r e n c e. th e ad73 22 wi ll en t e r a u t o s t a n d b y m o de a t t h e en d o f t h e c o n v er s i o n a f t e r t h e c o n t rol re g i st e r i s up d a t e d. 0 0 n o r m al m o de , a l l i n te r n a l c i rc u i t r y i s p o we re d up a t a l l t i m e s . table 11. sequ encer selection s e q 1 s e q 2 s e q u e n c e t y p e 0 0 the c h ann e l seque nc er is n o t used. th e an alog ch annel selected by programmi ng the add0 bit in the cont rol regist er sele cts the next chan nel f o r c onve r sio n . 1 0 this configu r ation is used in conju n ction with the ch a n nel address bit in the cont ro l re gister . pr o v ide d th at the cha n nel address bit is 1, the adc will convert firs tly on channel 0 then chan nel 1 and will repeat this seque nc e until the seq bits are chang e d in the c ontr o l re gister. 1 1 the c h ann e l seque nc er is n o t used. th e an alog ch annel selected by programmi ng the add0 bit in the cont rol regist er sele cts the next chan nel f o r c onve r sio n . r e v. pr e | pa g e 13 o f 18
ad7322 preliminary technical data ran g e regi s t er the r a n g e r e g i st er t o us e d t o s e le c t o n e analog in p u t r a n g e p e r analog in p u t cha n n e l . i t is a 4 - bi t wr i t e o n l y r e g i s t er , w i t h t wo de dic a te d r a n g e b i t s fo r e a ch o f t h e tw o analog i n p u t c h a n n e ls. th er e a r e fo ur analog in p u t r a n g es t o ch o o s e f r o m , 10v , 5v , 2.5v , 0 t o 10v . a wr i t e t o t h e r a ng e reg i s t er is s e le c t e d b y s e t t in g t h e w r i t e b i t t o 1 a nd t h e reg i s t er s e le c t b i t t o 1. on ce t h e i n i t ia l wr i t e t o t h e r a n g e reg i st er o c c u rs th e ad7322 a u to ma tic a l l y co nf igur es th e tw o analog in p u ts t o th e a p p r o p r i a t e ra n g e , as in dic a ted b y the r a n g e r eg is t e r , eac h tim e an y o n e o f t h es e a n al og in p u t c h ann e ls is s e lec t ed . th e 10v in p u t r a n g e is s e lec t e d b y defa u l t on eac h a n alog in p u t chan nel. se e . ta b l e 1 2 table 12. r a ng e regist er wr i t e re g i ster se l e c t 1 re g i ster se l e c t 2 vi n 0 a v i n 0 b v i n 1 a v i n 1 b v i n x a v i nxb des c r i p t io n 0 0 this c o m b i n a t io n s e le c t s t h e 10v inp u t r a n g e on a n a l o g inp u t x . 0 1 this co m b in a t io n s e le c t s t h e 5v i n p u t ra n g e o n a n a l o g i n p u t x . 1 0 this co m b in a t io n s e le c t s t h e 2.5v inp u t r a n g e on a n a l o g inp u t x . 1 1 this co m b in a t io n s e le c t s t h e 0 to 10v inp u t r a n g e on a n a l o g inp u t x . r e v. pr e | pa g e 14 o f 18
ad7322 preliminary technical data reference the ad7322 can o p era t e wi t h ei th er t h e in ter n al 2.5v o n -chi p re f e re nc e or an e x te r n a l ly a p p l i e d re f e re nc e. t h e i n te r n a l r e fer e n c e is s e le c t e d b y s e t t ing t h e ref b i t in t h e c o n t r o l reg i st er t o 1. on p o w e r u p th e ref b i t wil l b e 0, s e lec t in g t h e ext e r n al ref e r e n c e f o r the ad7 322 co n v ersio n . f o r ext e r n al r e fer e n c e o p er a t io n t h e ref in /ref out p i n sh o u ld b e de co u p le d t o a g nd wi th a 470 nf c a p a ci to r . the in t e r n al ref e r e n c e cir c ui tr y co n s is ts o f a 2.5v ban d g a p r e f e r e n c e an d a r e f e r e n c e b u f f er . w h en o p er a t ing th e ad7322 in in t e r n al refer e nce mo de t h e 2.5 v in ter n al r e fer e n c e is a v ai lab l e at t h e r e f in /re f ou t p i n. w h en usin g t h e ad73 22 wi t h t h e i n te r n a l re f e re n c e t h e r e f i n / r e f o u t pi n s h o u l d b e deco u p led t o a g nd usin g a 0. 47 f ca p . i t is r e co mmen d e d t h a t t h e i n t e r n a l refer e nce b e b u f f er e d b e fo r e a p pl yin g i t e l s e w h er e in t h e sys t em. the ad7322 is s p ecif ie d f o r a 2.5v t o 3v r e f e r e n c e ran g e . w h en a 3v r e fer e n c e i s s e le c t e d t h e ran g es wi l l b e , 12v , 6v , 3v a nd 0 t o 12v . f o r t h es e ra n g es t h e v dd a nd v ss su p p ly m u st b e eq ual t o o r gr ea t e r th a n t h e m a x a n al og i n p u t r a n g e s e l e ct e d . on p o w e r u p if t h e i n t e r n a l r e fe r e n c e op era t ion is r e q u ir e d fo r t h e ad c con v e r sio n , a wr i t e t o t h e con t r o l r e g i s t er is ne ces s a r y t o s e t t h e ref b i t t o 1. d u r i n g t h e c o n t r o l reg i s t er wr i t e t h e co n v ersio n r e s u l t f r o m t h e f i rs t ini t ial con v ersion w i l l b e i n vali d. the r e fer e n c e b u f f er wi l l r e q u ir e tbd us t o p o w e r u p a nd c h a r g e th e 0.47 f deco u p lin g c a p , d u r i n g t h e p o w e r u p tim e t h e con v ersio n res u l t f r o m t h e a d c wi l l b e i n val i d . r e v. pr e | pa g e 15 o f 18
ad7322 preliminary technical data modes of operation the ad7322 has a n u m b er o f dif f er en t m o des o f o p era t io n. th e s e m o des a r e desig n e d t o p r o v ide f l exi b le p o w e r m a n a ge me n t opt i ons . t h e s e opt i ons c a n b e c h o s e n to opt i m i z e th e p o w e r d i s s i p a t io n/thr o ugh p u t ra te ra tio f o r th e d i f f er in g a p plic a t ion r e quir em e n ts. t h e m o d e o f o p era t i o n o f t h e ad7322 is co n t r o l l ed b y th e p o w e r m a na gem e n t b i ts, pm1 and p m 0 , i n t h e c o n t ro l re g i ste r a s d e t a i l e d i n .the def a u l t m o d e is n o r m a l m o de , w h er e a l l in t e r n a l cir c ui t r y is f u l l y po w e r e d u p . ta b l e 1 0 n o r m a l m o d e ( p m1 = pm0 = 0) this m o d e is in t e nde d fo r t h e f a st est t h r o ug h p u t ra t e p e r f o r ma n c e , the ad7322 is f u l l y p o w e r e d u p a t al l tim e s. show s t h e ge ne r a l d i a g r a m of op e r a t i o n of t h e ad7322 in n o r m al m o de . f i g u re 1 3 f i g u re 13. no r m a l m o de t h e c o n v e r s i on i s i n it i a te d on t h e f a l l i n g e d g e of cs and t h e t r ack an d h o ld wi l l e n t e r h o ld m o d e as de s c r i b e d i n t h e s e r i a l i n t e r f ace s e c t ion. th e d a t a o n t h e d i n li n e d u r i n g t h e 16 sc l k tra n sf er wil l b e lo aded in t o on e o f th e o n -c hi p reg i s t ers, p r o v ide d t h e w r i t e b i t is s e t. the r e g i s t er is s e le c t e d b y p r og ra mmin g t h e reg i s t er s e le c t b i ts, s e e t a b l e 1 o f t h e r e g i s t e r secti o n . the ad7322 wi l l r e ma in f u l l y p o w e r e d u p a t t h e end o f the co n v ersio n p r o v ided bo th pm1 a nd pm0 con t a i n 0 in t h e co n t r o l reg i s t er . sixt e e n s e r i al cl o c k c y cles a r e r e q u ir e d t o co m p let e t h e co n v ersio n an d acces s t h e con v ersio n r e s u l t . a t t h e e nd o f t h e co n v ersio n cs ma y idle hig h u n til th e n e xt con v ersio n o r ma y idle lo w un til s o m e t i m e p r io r t o th e n e xt con v ersio n . on ce t h e da t a t r a n sf er is co m p let e , an o t her co n v ersio n can b e i n i t i a te d af te r t h e qu i e t t i me, t quiet , h a s e l a p s e d . f u l l sh ut d o w n m o de (pm1 = pm0 = 1) i n this m o de al l in t e r n al cir c ui t r y o n th e ad73 22 is p o w e r e d do wn. t h e p a r t r e t a in s info r m a t io n i n t h e r e g i st ers d u r i n g f u l l s h u t do wn. th e ad7322 r e ma ins in f u l l s h u t do wn m o de u n til t h e p o w e r ma nag e m e n t s b i ts i n t h e c o n t r o l reg i s t er , pm1 a nd p m 0 , are ch ang e d. i f a wr i t e t o t h e co n t r o l r e g i s t er o c c u rs w h ile t h e p a r t is in f u l l sh u t do w n m o d e , wi t h t h e p o w e r ma na ge m e n t b i ts, pm1 an d pm0 s e t t o 0, n o r m al m o de , th e p a r t wil l b e g i n to p o w e r u p o n th e cs ri s i n g ed g e . t o en s u r e t h e ad7322 is f u l l y p o w e r e d u p , t po w e r up , s h o u l d el a p s e b e fore t h e ne x t cs falling edg e . a u t o sh ut do w n m o de (p m1 = 1, pm0 = 0) on ce t h e a u t o s h u t down m o de is s e lec t e d t h e ad7322 wil l a u t o ma t i cal l y en t e r sh u t down a t t h e e nd o f e a ch con v ersio n . the ad7322 r e t a in s inf o r m a t ion in t h e reg i s t ers d u r i n g sh u t down. t h e t r ack-and- h o ld is in h o ld d u r i ng sh u t do w n . on th e fallin g cs ed g e , th e tra c k- a n d-h o ld tha t w a s i n h o ld d u ri n g s h u t d o wn will r e t u rn t o tra c k . the p o wer - u p f r o m a u to sh utd o wn is tbd s i n this m o de t h e p o w e r co n s u m p t ion o f th e ad7322 is g r ea tl y r e d u ce d w i t h t h e p a r t en t e r i n g sh u t down a t t h e end o f e a ch co n v ersio n . w h en t h e co n t r o l r e g i s t ers is p r og ra mm e d t o m o ve i n t o a u t o s h u t do w n m o de , i t do es so a t t h e en d o f th e co n v ersio n . a u t o s t a n db y m o de (pm 1 = 0, pm0 =1) i n a u t o s t an d b y m o de p o r t io ns o f th e ad7322 a r e p o w e r e d d o w n but t h e o n - c h i p re f e re nc e re m a i n s p o we re d up . t h e re f e re nc e bit i n t h e c o n t ro l re g i ste r s h ou l d b e 0 to e n su re t h e o n -ch i p r e fer e nce is ena b le d . t h is m o de is sim i la r t o a u t o s h u t down b u t a l lo ws th e ad73 22 t o p o w e r u p m u c h fas t er , al lo win g fast er thr o ug h p u t ra t e s t o be ac hieved . the ad7322 wi l l en t e r s t and b y a t t h e end o f the co n v ersion. the p a r t r e t a in s info r m a t io n i n t h e reg i st ers d u r i n g s t a n d b y . the ad7322 wi l l r e ma in in s t and b y un til i t r e c e i v es a cs fallin g ed g e . th e a d c w i ll be gin t o po w e r u p o n th e cs fal l in g edge . on t h is cs fa l l in g e d ge t h e t r ack-and- h o ld t h a t wa s in h o ld m o d e w h i l e t h e p a r t was in s t and b y w i l l r e t u r n to t r ack. w a k e - up t i m e f r om st an dby i s 1 s . t h e u s e r s h ou l d e n s u re t h a t 1 s has el a p s e d b e fo r e a ttem p t i n g a va lid con v ersio n . w h en r u nni n g th e ad7322 wi th the maxim u m 20 mh z sclk, o n e d u mm y co n v ersio n o f 1 6 x sclks is s u f f icien t t o p o w e r u p th e ad c. this d u mm y co n v ersio n ef fe c t iv e l y hal v es t h e t h r o ug h p u t ra t e o f th e ad7322, wi t h ev er y s e co nd con v ersio n res u l t b e in g a va lid r e su l t . o n ce a u to s t and b y m o de is s e le c t e d , t h e a d c c a n m o v e i n an d o u t o f t h e lo w p o w e r s t a t e b y co n t rol l in g t h e cs sig n al . r e v. pr e | pa g e 16 o f 18
ad7322 preliminary technical data serial interface f i gur e 1 4 f i gur e 1 4 . ser i a l int e r f ac e timi ng d i agr a m ( c o n t r ol r e g i st e r wr it e ) s h o w s th e tim i n g di a g ra m f o r th e se rial i n t e rfa c e o f th e ad7322. th e s e r i al c l o c k a p p l ied t o t h e sclk p i n p r o v ides t h e con v ersio n clo c k an d als o c o n t r o ls t h e t r a n sfer o f inf o r m a t io n t o a nd f r o m the ad7322 d u r i n g a co n v ersio n . the cs sig n al ini t i a t e s t h e da t a t r an sfer a n d t h e con v ersio n p r oc e s s . th e falli n g ed g e o f cs p u ts th e tra c k - a n d - h o ld in t o h o ld m o de , t a k e t h e b u s o u t o f t h r e e-s t a t e an d t h e analog in p u t sig n a l is s a m p le d a t t h is p o i n t. on ce t h e con v e r sio n is ini t i a t e d i t wil l r e q u ir e 1 6 sclk c y c l es t o co m p let e . the t r ack - an d - h o ld wi l l go b a ck in t o t r ack o n t h e 15t h scl k fal l in g edge . on th e sixteen t h s c lk fal l ing edge , th e d o ut line wil l r e t u r n t o thr e e-s t a t e . i f t h e r i sin g edg e o f cs oc cu r s be f o r e 16 sclk c y cles ha v e el a p s e d , t h e co n v ersion w i l l b e t e r m i n a t e d , t h e d o u t li n e wi l l r e t u r n to t h r e e-st a t e, and de p e ndi n g o n w h en t h e cs s i gn al i s b r o u gh t hi g h th e a d d r e s sed r e gi s t e r m a y o r ma y n o t be u p da ted . d a t a is c l o c k e d in t o the ad7322 on the sclk fal l i n g e d g e . the t h r e e m s b o n t h e d i n line a r e de co de d t o s e le c t w h ich r e g i st er is b e in g addr ess e d . t h e c o n t r o l reg i st e r is a n e l e v en b i t r e g i s t er , if t h e c o n t r o l r e g i s t er i s addr es s e d b y t h e t h r e e ms b , t h e da t a on t h e d i n li n e wi l l b e lo ade d in t o t h e co n t r o l o n t h e 1 5 th sclk fal l i n g e d g e . i f t h e r a n g e r e g i s t ers is addr es s e d t h e da t a on t h e d i n line w i l l b e lo ade d i n t o t h e addr es s e d r e g i s t er o n t h e 11 th s c lk fal l ing edge . c o n v ersio n da t a is c l o c k e d o u t o f th e ad7322 o n eac h s c lk fal l in g edge . d a ta o n t h e d o ut lin e wil l co n s is t o f tw o leading zer o s, a cha n n e l iden t i f i er b i t, a sig n b i t and t h e 12-b i t co n v ersio n r e s u l t . th e channe l i d en t i f i er b i t is u s e d t o i ndic a te w h ich cha n n e l t h e con v ersion r e s u l t co r r es p o nds t o . r e v. pr e | pa g e 17 o f 18
ad7322 preliminary technical data outline dimensions 14-l e ad thin shrin k sma l l o u tline (t sso p) (ru-14) or d e ri ng gui d e ad73 22 prod ucts temperature p a ckage package descri ption package outlin e ad7322bru C40c to +85c tssop ru-14 eval-ad7322c b 1 e v a l u a t i o n bo ar d eval-control brd2 2 c o n t r o l l e r boar d notes 1 th i s ca n be u s e d a s a st a n d- a l on e ev a l ua t i on boa r d or i n con j u n c t i on wi th t h e eval- c on tr ol boa r d for eva l ua t i o n /dem on st ra t i on purpose s . 2 this board is a compl e te unit al lowing a p c t o con t r o l a n d com m u n i ca t e wi t h a ll an a l og d e vi ce s eva l ua t i on boa r ds en di n g i n t h e c b de s i gnato r s . to o r der a co mple te evaluation kit, the particular adc evaluation board, e .g., eval-ad7322cb , t h e ev al-control b rd2, and a 12v tra n sformer must b e o r der e d. se e r e l e va n t eva l ua t i on bo ard te chnical note f o r more inf o rmation. esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity. r e v. pr e | pa g e 18 o f 18

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